The present invention relates to a semiconductor memory device, and in particular to a deep trench dynamic random access memory (DRAM) capacitor structure wherein a temperature sensitive high dielectric constant material is used and is incorporated into the storage node of the DRAM trench capacitor.
In dynamic random access memory (DRAM) cell manufacturing, a key issue is the size of the overall cell. As the integration densities increase, it is desirable in the semiconductor industry to decrease the storage capacitor size while maintaining the charge storage capacity. One approach to this problem in the prior art is to utilize a deep trench capacitor. Such capacitor structures have reduced surface space while maintaining the charge storage capacity of the capacitor.
One problem associated with the formation of deep trench capacitors for semiconductor memory cells such as DRAMs is how to incorporate temperature sensitive high dielectric constant materials such as barium strontium titanium oxide (BSTO) into the storage node of the DRAM capacitor device.
Another problem associated with the formation of deep trench storage capacitors is the effect of the buried-strap outdiffusion on the array MOSFET electrical characteristics. Presently, DRAM technology falls into two main categories, use of stacked capacitor storage elements and use of deep trench storage capacitors. Each approach has certain advantages and disadvantages relative to each other. For example, deep trench technology results in improved planarization of the various layers of the structure which facilitates the ultra-fine lithographic and etching processes required for todays DRAMs.
FIG. 1 is a cross-sectional diagram showing the structure of a prior art DRAM cell 61 having a trench storage capacitor 60 and an array MOSFET 62. The DRAM cell 61 occupies an area of about 7F2 of the surface area of the DRAM IC, F being the minimum feature size which is photolithographically defined for features on the IC. The DRAM cell 61 is characterized by a design dimension 63 which is defined as the lateral distance between the near edge 64 of the trench storage capacitor 60 and the far edge 66 of the gate conductor 68. In an existing 7F2 DRAM cell design, this dimension 63 is designed to have a value of nominally 1.5 F., with the width of the gate conductor being 1.0 F. and the nominal (designed) distance between the near edge of the gate conductor and the trench storage capacitor 60 being 0.5 F.
The most widely used trench storage DRAM technology utilizes a buried-strap (see FIG. 1) to form the connection between the array MOSFET and the storage capacitor 60. The buried-strap has a diffusion associated with it which extends vertically and laterally away from the interfacial opening between the trench storage capacitor 60 and the silicon substrate (see FIG. 1). The diffusion is formed by the outdiffusion of dopants (i.e. arsenic) from the N+ polysilicon in the storage trench into the adjacent single crystal silicon substrate. The depth and lateral extent of this buried-strap outdiffusion is highly detrimental to the scalability of the array MOSFET.
In past DRAM generations, when the state of the art minimum feature size, F, was larger than approximately 0.5 xcexcm, the presence of the buried-strap outdiffusion did not pose much of an electrical problem for the array MOSFET. However, with present day DRAM designs approaching minimum feature size equal to 0.15 xcexcm, and the typical buried-strap outdiffusion distance being greater than 50 nm from the interface between the N+ polysilicon in the deep trench, it is likely that the buried-strap outdiffused junction may extend under the gate conductor (wordline). This is likely to occur since, in addition to the large outdiffusion relative to the dimension 63, there is significant misalignment tolerance between the gate conductor and the deep storage trench. As shown in FIG. 1, the encroachment of the buried-strap outdiffusion upon the array MOSFET is characterized by the parameter xcex4, which is the distance between the bitline (BL) diffusion and the buried-strap (BS) outdiffusion, expressed as a percentage of the trench edge to gate conductor edge dimension 63.
FIG. 2 illustrates how the device off-current increases with decreasing xcex4. To assure that the off-current objective is met under all circumstances, the channel doping of the MOSFET must be raised. However, increased channel doping results in increased junction leakage and degraded device performance, thus degrading data retention time. Therefore, it is highly desirable to make the value of xcex4 as large as possible to minimize these deleterious effects.
The distance between the bitline diffusion and the buried-strap diffusion is determined by the layout ground rules, process tolerances (overlay and feature size) and the amount of buried-strap outdiffusion from the trench storage capacitor. This critical distance is illustrated by the parameter xcex4 in the prior art deep trench DRAM cell shown in FIG. 1. The amount of buried-strap outdiffusion is principally determined by the thermal budget that the buried-strap encounters in the course of the chip fabrication process. The thermal budget is a function of the square root of the sum of the products of the diffusivity, D, of the strap dopant impurity and the effective amount of time spent at each high temperature step which contributes significantly to the diffusion.
For prior art deep trench storage capacitor DRAM cells, the high temperature processing steps which contribute to the strap outdiffusion from the storage capacitor polysilicon typically consist of STI oxidation, STI densification, gate sacrificial oxidation, transfer gate oxidation, gate conductor sidewall oxidation, and junction anneals. The combined thermal budget of these high-temperature processes results in an arsenic outdiffusion from the storage trench poly into the silicon substrate which typically ranges from 50 to 100 nm. This means that for high-density trench DRAM cell designs having a minimum feature size of 0.15 xcexcm, the distance xcex4 typically ranges from 0.08 to 0.13 xcexcm; xcex4 typically ranges from 35% to 60% of the design distance between the storage trench edge and the far edge of the gate conductor, for prior art DRAM cells having a layout area of 7 minimum features squared (7F2) per bit and a minimum feature size, F, equal to 0.15 xcexcm. As seen from FIG. 2, the off-current can vary by more than 100xc3x97 over this range of variation in xcex4.
In a possible fabrication approach, a deep trench is first formed in a semiconductor substrate or wafer and then the deep trench is filled with a temperature sensitive high dielectric constant material. After filling the deep trench with the temperature sensitive high dielectric constant material, shallow trench isolation (STI) regions and gate conductor (GC) stacks are typically formed. A problem with such an approach is that the high temperatures used in fabricating the STI regions and the GC stacks adversely affect the temperature sensitive high dielectric constant material used in filling the deep trench and contribute to the buried-strap outdiffusion. Specifically, the length of time at the high processing temperatures employed in fabricating the STI regions and the GC stacks cause decomposition of the temperature sensitive high dielectric constant material and add to the thermal budget of the strap outdiffusion. The high dielectric material and its by-products thus formed may diffuse and interact with the underlying semiconductor material.
To avoid this problem of capacitor insulator degradation, the prior art in stacked capacitor DRAM technology utilizes a thin electrically conductive barrier layer comprising a material such as TiN, TiAlN, TaSiN and CoSi between the temperature sensitive high dielectric constant material and the semiconductor material, e.g. silicon. The presence of such a barrier layer in semiconductor memory devices, while prohibiting oxygen diffusion from occurring, adds additional processing steps and costs to the overall semiconductor memory device manufacturing process.
On top of this conductive barrier layer, the prior art in stacked capacitor DRAM technology typically deposits a thin layer of a conductive material so as to form a bottom electrode. This conducting layer, in the case of high dielectric constant capacitors, is composed of conductive oxides such as RuO2, SrRuO3, Laxe2x80x94Srxe2x80x94Coxe2x80x94O and IrO2, or by metals like Pt or Ir. One advantage of SrRuO3 is that it can be directly deposited on silicon with minimum or no oxidation underneath. A high dielectric constant material can then be deposited on top of the electrode layer to a desired thickness.
Finally, for the top electrodes, material similar to the bottom electrode is typically selected. If it is desired to use a polysilicon or amorphous silicon overlayer, a thin layer of a barrier material, as discussed above, can be deposited to prevent undesirable reactions between silicon and the electrode material before chemical vapor deposition (LPCVD) of amorphous/polysilicon.
In view of the drawbacks mentioned with prior DRAM stacked capacitor structures in using temperature sensitive high dielectric constant material, it would be beneficial if a new and improved process of fabricating a trench DRAM capacitor structure having a temperature sensitive high dielectric constant material incorporated into the storage node of the DRAM capacitor structure was developed which overcomes all of these drawbacks.
It should also be mentioned that in the process embodiment of the present invention, the buried-strap outdiffusion from the trench storage capacitor does not encounter the STI liner oxidation, sacrificial oxidation and gate oxidation steps. This limits the thermal budget and the amount of buried-strap outdiffusion. In prior art processes, the buried-strap diffuses further due to the inclusion of the three oxidation steps mentioned above.
One object of the present invention is to provide a process of fabricating a trench capacitor semiconductor memory device which allows for the easy incorporation of a temperature sensitive high dielectric constant material into the capacitor region of the device.
Another object of the present invention is to provide a process of fabricating a trench capacitor semiconductor memory device wherein the storage node material, i.e. temperature sensitive high dielectric constant material, does not degrade during the course of providing the STI regions and the GC stack regions of the memory device.
A still further aspect of the present invention is to provide a process of fabricating a trench capacitor semiconductor memory cell device wherein the temperature sensitive high dielectric constant material does not diffuse into the underlying semiconductor material.
Yet another object of the present invention is to provide a process which results in a limited buried-strap outdiffusion, whose deleterious electrical effects on the array MOSFET are reduced from the prior art.
These as well as other objects and advantages can be achieved in the present invention by forming the storage trench after formation of the STI regions in a semiconductor structure which contains preformed layers of a partial GC stack already on the surface of the structure. By fabricating the trench capacitor after STI formation, the temperature sensitive high dielectric constant material does not encounter the high temperatures associated with STI formation. Moreover, since the initial structure contains a partial GC stack already on the surface, the temperature sensitive high dielectric constant material does not encounter high temperatures that are associated with fabricating the GC stack; therefore substantially no degradation of the temperature sensitive material is caused to occur.
Specifically, the process of the present invention comprises the steps of:
(a) providing a semiconductor structure comprising a semiconductor substrate or wafer having at least one trench storage region and a raised shallow trench isolation (STI) region adjacent to said trench storage region, said structure having preformed layers of a partial gate conductor stack formed on said substrate or wafer which are spaced apart by said trench storage region and said raised STI region;
(b) forming a bottom electrode in said trench storage region;
(c) forming a temperature sensitive high dielectric constant material on said bottom electrode and lining sidewalls of said trench storage region;
(d) forming a top electrode over said temperature sensitive high dielectric constant material;
(e) filling said trench with polysilicon;
(f) completing fabrication of a capacitor in said trench storage region;
(g) forming a patterned gate conductor region from said preformed GC stack layers; and
(h) forming subsequent device connections so as to complete fabrication of a trench capacitor semiconductor memory cell.
In a highly preferred embodiment of the present invention, the trench storage region is formed after STI formation and formation of the partial GC stack layers. In another highly preferred embodiment of the present invention, a conducting barrier layer is formed over the top electrode prior to the polysilicon fill.
In accordance with the present invention, the formation of the trench storage capacitor follows the formation of the STI. This means that the prior art high-temperature processing steps which include STI oxidation, STI densification, gate sacrificial oxidation, and transfer gate oxidation are not seen by the buried-strap outdiffusion. Elimination of these high temperature steps from the thermal budget of the strap outdiffusion typically results in a reduction of thermal budget of greater than 50%. This reduction of thermal budget translates into a reduction of strap outdiffusion which is typically greater than 30% of the outdiffused distance which results from the prior art process. This reduction in strap outdiffusion, which is typically less than 50 nm, results in a substantial increase in the parameter xcex4, which results in reduced off-current for a given channel doping concentration. In the present invention xcex4 is always greater than that of the prior art structures. For the inventive structure, xcex4 is typically 50% to greater than 75% of the design distance between the storage trench edge and the far edge of the gate conductor, for a 7F2 cell with F=0.15 xcexcm. Because of the high sensitivity of the MOSFET off-current to xcex4, the inventive structure represents a significant improvement over the prior art, whose xcex4 ranges from 35% to 60% of the design distance.